1. Field of the Invention
This invention relates to a variable-speed controller for use in a computer. More particularly, the invention relates to using a variable speed controller to increase the speed of selected operations.
2. Description of Prior Art
Modern personal computers have undergone significant performance improvements during the past decade. These increases in performance have been driven primarily by performance increases of several orders of magnitude in the x86 family of microprocessors. Intel's original 8086 processor was succeeded by the 80286 microprocessor, which was succeeded by the 80386, and then by the 80486. The most recent addition to the x86 family of microprocessors is Intel's Pentium. Each generation of the x86 processors significantly improved the speed and capabilities of the previous generation. Although the original 8086 processor was designed in the late seventies, designers developing systems based on later-generation x86 microprocessors have always been careful to retain software-compatibility with the original 8086 architecture.
The 8086 uses a segmented addressing mechanism whereby a 16-bit segment register is combined with a 16-bit offset in a manner that results in a 20-bit physical address. This 20-bit address enables one megabyte (2.sup.20) of memory to be addressed in sixteen 64-Kbyte segments. Since segments are 64-Kbytes in length, a segment starting at 00000 hex, for example, extends to 0FFFF hex. And because an 8086 physical address is only twenty bits long, segments that start within 64-Kbytes of the top of the one megabyte address space will wrap-around to the bottom of the address space once the one megabyte boundary is reached. To illustrate this concept, consider a 64-Kbyte segment that begins at FFF00 hex. The "end" of this segment is at 0FEFF hex: the segment extends from FFF00 hex to FFFFF hex, and then wraps around the one megabyte boundary and runs from 00000 hex to 0FEFF hex.
With the 80286 microprocessor, however, Intel designed a new address mapping scheme called "protected" mode. The protected mode addressing scheme was Intel's attempt to provide a robust means by which several programs can be executed at once. In 80286 protected mode, the segment register is used in a manner that increases the physical address length from 20 bits to 24 bits. This twenty-four bit physical address enables 16 megabytes to be addressed, as opposed to the one megabyte address space for the 8086. In addition, the later-introduced 80386, 80486 and Pentium processors have a 32-bit physical address, enabling 4 gigabytes of memory to be addressed. Because the 80286 and higher processors have a physical address wider than 20 bits, a 64-Kbyte segment that begins within 64-Kbytes of the one megabyte boundary will not wrap-around at the one megabyte boundary. For example, an address that begins at FFF00 hex will extend to 10FEFF hex. Thus, because addresses 100000 hex and higher can be expressed in a 24- or 32-bit address, wrap-around at the one-megabyte boundary will not occur in the 80286, 80386, 80486, and Pentium processors. This functional difference renders software written for the 8086 incompatible with the protected mode operation of the 80286, 80386, 80486, and Pentium processors.
To maintain compatibility with software written for the original 8086 architecture, 80286 and higher microprocessors have a "real mode" capability in which they behave like an 8086 processor. Even when in real mode, however, the wrap-around operation at the one megabyte boundary described above is not duplicated. To duplicate the one megabyte boundary wrap-around operation of the 8086 microprocessor, the address line for the twentieth bit (A20 line) must be forced low by logic external to the microprocessor. If the twentieth address line (A20) is forced low in appropriate circumstances, the 80286, 80386, 80486, and Pentium processors simulate the 8086 one-megabyte boundary wrap-around, thereby maintaining compatibility with software written for the 8086 processor.
The prevailing method developed by the industry for forcing the A20 line low involves generating a MASK-A20 signal. When this MASK-A20 signal is activated, the address line for the twentieth address bit is forced low, which will then result in a wrap-around at the one-megabyte boundary. The MASK-A20 signal is generated using an extra, unused pin on the 8042 keyboard controller. FIG. 1 shows a general diagram of a prior art system. The 8042-based method of generating the MASK-A20 signal requires little or no extra hardware, and this solution was somewhat convenient when it was devised. Yet it is now clear that using the 8042 for generating the MASK-A20 signal in the manner shown in FIG. 1 is very slow and inefficient. Activating and deactivating the MASK-A20 signal in this manner requires that a command be sent to the 8042 controller 31, which then executes a routine to carry out the MASK-A20 command. Although this design is clumsy, there are obstacles to simply casting this design aside in favor of a better design. A large amount of software has been written that relies on the assumption that the MASK-A20 signal is controlled by the 8042 controller 31. Retaining compatibility with this existing software therefore requires hardware compatible with the 8042-based arrangement.
Like the MASK-A20 signal, a RESET-CPU signal has also been controlled by an extra, unused pin on the 8042 keyboard controller 31. The RESET-CPU signal is used to reset the microprocessor. One purpose of resetting the microprocessor is to switch from protected mode to real mode in an x86-based system. Resetting the system automatically puts the microprocessor in real mode, the default operating mode. Once the system is reset, the resetting program regains control of the CPU, and thereafter executes in real mode. Unlike the 80386 and higher processors based on the x86 architecture, the 80286 does not have a specific instruction for switching from protected mode to real mode. This 8042-based solution was devised to simulate such an instruction in the 80286. As a result, software was developed for the 80286 based on the assumption that the RESET-CPU function was controlled by the 8042. And like the MASK-A20 function, controlling the RESET-CPU signal with the 8042 is slow, but retaining compatibility with existing 80286 software requires hardware compatible with this 8042-based arrangement.
Attempts have been made to improve the 8042-based procedure for controlling the MASK-A20 and RESET-CPU signals. Installing a separate hardware port for these functions and using logic other than the 8042 to perform the task of generating the MASK-A20 and/or RESET-CPU signals are proposed solutions. These implementations, however, result in a system incompatible with existing software. Another proposal was made in U.S. Pat. No. 5,226,122, issued to Thayer et al., to which reference may be had for a further description of the conventional 8042 -based implementation, described above. Thayer et al. disclosed the use of one or more programmable logic arrays or gate arrays for regulating slow commands in place of allowing the 8042 to control the commands. See FIG. 2. This solution retains compatibility with 8086-based software, but is relatively expensive and has not been widely implemented.
What is needed, therefore, is a method or apparatus for increasing the speed of the MASK-A20 and RESET-CPU commands, while maintaining full compatibility with existing 8086 software that uses the 8042 keyboard controller to change the MASK-A20 signal.